LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity linebuffer is
  port (clk : in std_logic;
		rstn : in std_logic;
		
		addr_1 : in std_logic_vector(8 downto 0);
		r_1 : out std_logic_vector(7 downto 0);
		g_1 : out std_logic_vector(7 downto 0);
		b_1 : out std_logic_vector(7 downto 0);
		
		addr_2 : in std_logic_vector(8 downto 0);
		r_2 : out std_logic_vector(7 downto 0);
		g_2 : out std_logic_vector(7 downto 0);
		b_2 : out std_logic_vector(7 downto 0);
		
		addr_w : in std_logic_vector(8 downto 0);
		r_w : in std_logic_vector(7 downto 0);
		g_w : in std_logic_vector(7 downto 0);
		b_w : in std_logic_vector(7 downto 0);
		w_en : in std_logic);
end entity;

architecture rtl of linebuffer is
	type memory is array(integer range<>) of std_logic_vector(23 downto 0);
	signal pixels : memory(319 downto 0);
	signal ctr : unsigned(9 downto 0);
begin
	process(addr_1, clk)
	begin
		if (rising_edge(clk)) then
			r_1 <= pixels(to_integer(unsigned(addr_1))) (7 downto 0);
			g_1 <= pixels(to_integer(unsigned(addr_1))) (15 downto 8);
			b_1 <= pixels(to_integer(unsigned(addr_1))) (23 downto 16);
		end if;
	end process;
	
	process(clk, addr_w, r_w, g_w, b_w)
	begin
		if (rising_edge(clk)) then
			if (unsigned(addr_w) < 320) and w_en = '1' then
				pixels(to_integer(unsigned(addr_w))) <= b_w & g_w & r_w;
			end if;
		end if;
	end process;

	process(addr_2, clk)
	begin
		if (rising_edge(clk)) then
			r_2 <= pixels(to_integer(unsigned(addr_2))) (7 downto 0);
			g_2 <= pixels(to_integer(unsigned(addr_2))) (15 downto 8);
			b_2 <= pixels(to_integer(unsigned(addr_2))) (23 downto 16);
		end if;
	end process;
end rtl;
